![verilog HDLBits刷题[Finite State Machines]“Exams/2014 q6b”---Q6b:FSM next-state logic](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Finite State Machines]“Exams/2014 q6b”---Q6b:FSM next-state logic)
1、题目Consider the state machine shown below, which has one inputwand one outputz.Assume that you wish to implement the FSM using three flip-flops and state codesy[3:1] 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flopy[2].Implement just the next-state logic fory[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)2、分析照图说话嘛最后推导Y2的下一状态的表达式3、代码module top_module ( input [3:1] y, input w, output Y2); parameter A3b000,B3b001,C3b010,D3b011,E3b100,F3b101; reg [2:0]next_state; always(*)begin case(y) A: next_statew?A:B; B:next_statew?D:C; C:next_statew?D:E; D:next_statew?A:F; E:next_statew?D:E; F:next_statew?D:C; default:next_stateA; endcase end assign Y2next_state[1]; endmodule
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