1、时钟端口不匹配原因RTLsys_clk_p / sys_clk_n XDCSYS_CLK0_P / SYS_CLK0_N在 cheshire_top_xilinx.sv 端口定义处ifdef TARGET_U280 input logic SYS_CLK0_P, input logic SYS_CLK0_N, else input logic sys_clk_p, input logic sys_clk_n, endif在 IBUFDS 处ifdef TARGET_U280 IBUFDS #( .IBUF_LOW_PWR (FALSE) ) i_bufds_sys_clk ( .I ( SYS_CLK0_P ), .IB ( SYS_CLK0_N ), .O ( sys_clk ) ); else IBUFDS #( .IBUF_LOW_PWR (FALSE) ) i_bufds_sys_clk ( .I ( sys_clk_p ), .IB ( sys_clk_n ), .O ( sys_clk ) ); endif2、修改impl_ip.tclclkwiz: u280 { set_property -dict [list \ CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ CONFIG.RESET_BOARD_INTERFACE {Custom} \ CONFIG.USE_RESET {true} \ CONFIG.PRIM_SOURCE {No_buffer} \ CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT1_USED {true} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLK_OUT1_PORT {clk_50} \ CONFIG.CLK_OUT2_PORT {clk_48} \ CONFIG.CLK_OUT3_PORT {clk_20} \ CONFIG.CLK_OUT4_PORT {clk_10} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {48.000} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ CONFIG.MMCM_CLKFBOUT_MULT_F {12.000} \ CONFIG.MMCM_CLKIN1_PERIOD {10.000} \ // 由5修改为10 CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ CONFIG.MMCM_CLKOUT2_DIVIDE {25} \ CONFIG.MMCM_CLKOUT3_DIVIDE {60} \ CONFIG.MMCM_CLKOUT4_DIVIDE {120} \ CONFIG.NUM_OUT_CLKS {4} \ ] [get_ips $proj] }3、时序检查发现存在负裕量构建脚本主动退出。修改dram_wrapper_xilinxifdef TARGET_U280 (* ASYNC_REG TRUE *) logic [1:0] mig_aresetn_sync_q; logic mig_aresetn; always_ff (posedge dram_axi_clk or negedge soc_resetn_i) begin if (!soc_resetn_i) mig_aresetn_sync_q 2b00; else mig_aresetn_sync_q {mig_aresetn_sync_q[0], 1b1}; end assign mig_aresetn mig_aresetn_sync_q[1]; endif ifdef TARGET_U280 .c0_ddr4_aresetn ( mig_aresetn ), else .c0_ddr4_aresetn ( soc_resetn_i ), endif //.c0_ddr4_aresetn ( soc_resetn_i ),4、DRC报错1u280.xdc中uart 端口与顶层uart端口命名不一致修改u280.xdc与顶层保持一致set_property PACKAGE_PIN A28 [get_ports uart_tx_o] set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o] set_property PACKAGE_PIN B33 [get_ports uart_rx_i] set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i]2u280无 jtag 端口注释掉phy_definition.svh中JTAG相关的参数ifdef TARGET_U280 define USE_RESET //define USE_JTAG //define USE_JTAG_VDDGND3u280.xdc中sys_reset 端口与顶层命名不一致修改顶层ifdef USE_RESET ifdef TARGET_U280 input logic CPU_RESET_FPGA, else input logic sys_reset, endif endif logic sys_reset_int; ifdef TARGET_U280 assign sys_reset_int ~CPU_RESET_FPGA; else assign sys_reset_int sys_reset; endif // Select SoC reset ifdef USE_RESET logic sys_resetn; assign sys_resetn ~sys_reset_int; elsif USE_RESETN logic sys_reset; assign sys_reset ~sys_resetn; endif